In the semiconductor industry, Moore's law states that the number of transistors on a chip doubles approximately every two years. These exponential performance gains present a challenge to the semiconductor manufacturing industry, along with the dual challenges of promoting power savings and providing cooling efficiency. The industry addresses these challenges in multiple ways. Selecting the gate dielectric and gate electrode are critical choices in enabling device scaling, and compatibility with CMOS technology. Two main approaches have emerged in high-k and metal gate (HKMG) integration: gate-first and gate-last. Gate-last is also called replacement metal gate (RMG) where the gate electrode is deposited after S/D junctions are formed and the high-k gate dielectric is deposited at the beginning of the process (high-k first).
A high-k first gate-last process is when the high-k dielectric is deposited first and the metal is deposited last (gate-last method). Gate-last is often referred to as the replacement gate option. “First” and “last”-gate denotes whether the metal gate electrode is deposited before or after the high temperature anneal process. Typically, the reliability of high-k gate stacks improve as a result of dopant activation anneal at a temperature of about 1000° C. However, this annealing process is only used for gate-first or high-k first, metal gate-last processes. The high-k last, metal gate-last process lacks such built-in high temperature treatment and thus reliability is a big challenge.
In the conventional process, if we want to apply a high thermal budget on high-k metals to improve reliability, the high-k metal layer needs to be formed prior to the dopant activation anneal (this is so-called gate-first process). The gate-first process typically requires robust encapsulation (using spacers) of the high-k metal gate stacks to prevent ambient oxygen to affect device characteristics. In addition, the high-k metal gate stack needs to be etched by RIE (reactive ion etching) at the time of gate patterning, which is typically challenging.
We provide a glossary of terms used throughout this disclosure:
Glossary.
k—dielectric constant value
high-k—having a ‘k’ value higher than 3.9 k, the dielectric constant of silicon dioxide
RTA—rapid thermal anneal.
A-Si—amorphous silicon
ALD—atomic layer deposition
CMOS—complementary metal-oxide semiconductor
FET—field effect transistor
FinFET—a fin-based, multigate FET
MOSFET—a metal-oxide semiconductor FET
PVD—physical vapor deposition
SiOx—silicon oxide
SiGe—silicon germanide
SiC—silicon carbide
RIE—reactive ion etching
ODL—optically dense layer; organically dielectric layer
STI—shallow trench isolation
S/D—source and drain terminals
NiSi—nickel silicide
C (DLC)—metal-free diamond-like carbon coating
SiN—silicon nitride
TDDB—time dependent dielectric breakdown
NBTI—negative bias temperature instability
PBTI—positive bias temperature instability
RTA—rapid thermal annealing
IL/HK—interfacial layer/high-k dielectric layer
TiN—titanium nitride
TiC—titanium carbide
TaN—tantalum nitride
TaC—tantalum carbide
TiAl—titanium aluminide
N2—nitrogen
Al—aluminide
W—tungsten